NBTI degradation effect on advanced-process 45 nm high-k PMOSFETs with geometric and process variations

Article history: Available online xxxx a b s t r a c t Negative bias temperature instability (NBTI) has become an important reliability concern for nano-scaled complementary metal oxide (CMOS) devices. This paper presents the effect of NBTI for a 45 nm advanced-process high-k dielectric with metal gate PMOS transistor. The device had incorporated advanced-process flow steps such as stress engineering and laser annealing in order to achieve high on-state drain current drive performance. To explore NBTI effects on an advanced-process sub-micron device, the 45 nm high-k PMOS transistor was simulated extensively with a wide range of geometric and process variations. The device was simulated at varying thicknesses in the dielectric layer, oxide interfacial layer, metal gate and polysilicon layer. In order to observe the NBTI effect on process variation, the NBTI degradation of the 45 nm advanced-process PMOS is compared with a 45 nm PMOS device which does not employ process induced stress and incorporates the conventional rapid thermal annealing (RTA) as compared to the laser annealing process which is integrated in the advanced-process device flow. The simulation results show increasing degradation trend in terms of the drain current and threshold voltage shift when the thicknesses of the dielectric layer, oxide layer as well as the metal gate are increased. Deep-sub-micron device scaling is a phenomenon which is rapidly evolving for ultra-scaled MOSFETs and the design of this technology requires stringent control of short-channel effects (SCE) and sub-threshold behavior. With this in mind, the gate dielectrics should be thinned to less than 1.0–1.5 nm equivalent oxide thickness (EOT) [1]. It has been reported that due to quantum mechanical tunnelling, the typical leakage current of SiO 2 at gate voltage, V g of 1 V can change from 10 À12 A/cm 2 with EOT of 3.5 nm to 10 A/cm 2 with EOT of 1.5 nm [2]. To achieve the EOT target stated above and to counter the issue of leakage currents, dielectric materials with higher permittivity, k values as compared to SiO 2 (k > 3.9) are introduced. Compounds of hafnium (Hf), zirconium (Zr), and aluminium (Al) have been proposed as potential high-k dielectric materials and hafnium oxide (HfO 2) has emerged as a promising gate dielectric to replace the conventional SiO 2 due its high dielectric constant (k = 25), wide bandgap (E 0 = 5.7 eV) [3], acceptable band offset with respect to silicon (DE c = …